FIGS. 9(a)-9(b) and 10(a)-10(b) are schematic diagrams illustrating a prior art high frequency and high output MMIC (Monolithic Microwave Integrated Circuit), in which FIG. 9(a) is a plan view, FIG. 9(b) is an enlarged view of a portion of FIG. 9(a), FIG. 10(a) is a cross-sectional view taken along line Xa--Xa of FIG. 9(a), and FIG. 10(b) is a cross-sectional view taken along line Xb--Xb of FIG. 9(b). Reference numeral 200 designates a GaAs MMIC chip including a plurality of active elements, such as field effect transistors (hereinafter referred to as FETs).
In FIG. 9(b), four drain electrodes 201a and four source electrodes 202a are alternatingly arranged in a line and a gate electrode 203a is disposed at every space between the drain and source electrodes. The drain electrodes 201a are connected to a common drain electrode 201 and the gate electrodes 203a are connected to a common gate electrode 203.
In FIG. 9(a), a pair of common drain electrodes 201 are connected to a drain bonding pad 221 via transmission lines 211, and a pair of common gate electrodes 203 are connected to a gate bonding pad 223 via transmission lines 213.
In FIGS. 10(a) and 10(b), an Au PHS 7 is disposed on the rear surface of the chip substrate 1 via a metal layer 5 which serves as a feeding layer when the Au PHS 7 is formed by electrolytic plating. The PHS 7 radiates heat generated by the elements on the surface of the chip substrate 1 to an underlying chip carrier (not shown) and mechanically supports the thin substrate 1, whereby the semiconductor IC chip is easily handled. The source electrodes 202a are connected to the Au PHS 7 via through-holes 2 penetrating the substrate 1 and the metal layer 5. The drain electrodes 201a, the common drain electrode 201, and the common gate electrodes 203 are omitted in FIG. 10(a).
A description is given of the production method.
FIGS. 11(a) to 11(f) are cross-sectional views taken along line Xa--Xa of FIG. 9(a) illustrating process steps in a method for producing the semiconductor chip.
Initially, active elements, such as FETs, transmission lines, and via-holes 2 are formed on chip regions of a GaAs wafer, which chip regions are separated from each other by chip separation lines, i.e., dicing lines (not shown). Thereafter, the surface of the wafer 10 is adhered to a glass plate 3 using wax 4, and the rear surface of the wafer is flattened by polishing until the thickness of the substrate becomes about 30 microns (FIG. 11(a)). Then, Au is applied to the rear surface of the wafer by vapor deposition or electroless plating to form an Au layer 5 which serves as a feeding layer when a PHS is plated in the subsequent process (FIG. 11(b)).
Then, a photoresist is applied to the feeding layer 5 to a thickness of about 40 microns and patterned leaving portions in place opposite the dicing lines on the surface of the wafer (FIG. 11(c)). Using the photoresist pattern 6 as a mask, an Au PHS 7 about 40 microns thick is formed on the rear surface of the wafer by electrolytic plating (FIG. 11(d)).
After removing the photoresist pattern 6 (FIG. 11(e)), the feeding layer 5 and the wafer 10 are selectively etched by wet etching using a mixture of sulfuric acid and hydrogen peroxide as an etchant and using the PHS 7 as a mask (FIG. 11(f)). In this way, the wafer 10 is divided into a plurality of semiconductor chips along the dicing lines.
Finally, the wax 4 is melted in a heated organic solvent to separate the semiconductor chips from the glass plate 3.
In the above-described production method of semiconductor chips, however, since the wafer 10 is divided into chips by etching during the wafer process, a test of high frequency characteristics of the respective semiconductor chips, which is usually performed with a grounding electrode on the rear surface of the wafer, is not performed automatically with respect to the wafer but performed manually with respect to each chip.
Furthermore, since the semiconductor chips are separated from each other after removing the glass plate 3, chip sorting, i.e., arrangement of semiconductor chips in the wafer according to characteristics of the respective chips, is not possible.
In order to solve the above-described problems, dicer cutting is employed to divide the wafer into chips. Figures 12(a) to 12(d) illustrate a method for producing semiconductor chips using the dicer cutting.
After adhering the GaAs wafer 10 to the glass plate 3 and forming the feeding layer 5 on the rear surface of the wafer (FIG. 12(a)), an Au PHS 7 about 40 microns thick is formed on the rear surface of the wafer by electroplating (FIG. 12(b)).
Then, the wax 4 is melted using a heated organic solvent to separate the glass plate 3 from the wafer 10, followed by cleaning (FIG. 12(c)). The wafer 10 is adhered to, for example, an expanded film (not shown) and then it is cut along the dicing lines using a dicing blade 8 (figure 12(d)), providing a semiconductor chip 200a.
In this method, since the dicer cutting of the wafer is carried out after separating the glass plate 3 from the wafer, the high frequency characteristic test can be performed before the dicer cutting. Furthermore, since the semiconductor chips after the dicing are adhered to the expanded film, chip sorting according to the results of the characteristics test can be performed.
During the dicer cutting, however, burrs 7a as long as the thickness of the Au PHS 7 are unfavorably produced on the rear surface of the chip 200a as shown in FIG. 13 due to the ductility of Au PHS 7. The burrs 7a cause an insufficient junction when the chip 200a is die-bonded on a chip carrier.
Furthermore, since the conventional semiconductor chips 200 and 200a unfavorably curve as shown in FIG. 14 regardless of the chip separation method, it is difficult to die-bond or wire-bond the chips onto the chip carrier. The curvature of the chip sometimes reduces the heat radiation characteristics and the RF characteristics of the chip. These problems will be described in more detail. FIG. 14 illustrates the semiconductor chip 200a mounted on the chip carrier 20. FIG. 15 is a graph illustrating the relation between the curvature of the semiconductor chip 200a and the length of the longer edge of the chip when the temperature of the chip is increased from 25.degree. C. to 300.degree. C. (temperature change .DELTA.t=275.degree. C.) during the die-bonding.
When the semiconductor chip 200a is adhered onto the chip carrier using Au-Sn alloy solder, the chip carrier is heated to the melting point of the solder, i.e., about 300.degree. C. Then, the chip 200a curves as shown in FIG. 14 due to the difference in thermal expansion coefficients between the substrate 1 and the Au PHS 7. It is well known that this curvature is calculated by the bimetal formula.
When the GaAs substrate 1 is about 30 microns thick, the Au PHS 7 is about 40 microns thick, and the temperature during the die-bonding is about 300.degree. C., the relation between the curvature (t) and the length of the longer edge (1) calculated by the bimetal formula is approximately equal to the relation shown in FIG. 15.
Therefore, as shown in FIG. 15, if the length (l) of the chip 200a exceeds 2.55 mm, die-bonding and wire-bonding of the chip on the chip carrier 20 are almost impossible. In addition, a decrease in the contact area between the chip and the chip carrier adversely affects the heat radiation characteristics, with a result that desired RF characteristics are not attained.
Furthermore, when the chip 200a with the curvature is adhered to the chip carrier 20 using a pellet of Au-Sn eutectic solder 9, since it is difficult to control the quantity of the melted solder 9, the chip 200a sometimes floats on the solder 9 which is as thick as the PHS 7, i.e., about 40-50 microns, adversely affecting the heat radiation characteristics and the RF characteristics.
Since the semiconductor chip 200a has the burrs 7a on the rear surface, the increase in the solder 9 is unavoidable.
Furthermore, since an oxide film is formed on the surface of the Au-Sn solder 9, it is necessary to rub the chip 200a against the chip carrier 20 to remove the oxide film and increase the adhesion of the solder 9 to the chip carrier 20. In this case, it is very difficult to die-bond the semiconductor chip on a narrow region of the chip carrier 20 with high precision.
Meanwhile, Japanese Published Patent Application No. 4-144157 discloses an improved method for producing semiconductor chips with no curvature. In this method, a radiating layer for radiating heat generated by an active element on a semiconductor substrate is formed on a part of the rear surface of the substrate directly opposite the active element, and a metal layer having a linear thermal expansion coefficient equal to that of the substrate and different from that of the radiating layer is formed on part of the rear surface of the substrate but not directly opposite the active element.
In this prior art method, however, since the metal layer is formed by dispersion plating, it is necessary to precisely control the composition of the plating solution. More specifically, during the dispersion plating, the linear thermal expansion coefficient of the plated layer is controlled by the rate of the dispersion medium to the plating solution, and the rate has to be increased to approximate the linear thermal expansion coefficient of the plated layer to that of the substrate. However, the increase in the rate of the dispersion medium to the plating solution adversely affects the electroplating. Therefore, it is very difficult to control the composition of the plating solution.
This prior art publication also discloses a process of alternatingly laminating a Mo film and a Ni film to produce the above-described plated metal layer. In this case, however, an Au film is needed between the Mo film and the Ni film to improve the adhesion between these films, resulting in a complicated process.
Meanwhile, Japanese Published Patent Application No. 3-232253 discloses another method for producing semiconductor chips, in which chip separation grooves, i.e., dicing grooves, are formed on a wafer by etching, the grooves are filled with Ni by electroless plating, Au PHS layers are selectively formed on the rear surface of the wafer opposite the regions where the grooves are absent, and the wafer is divided into a plurality of chips along the grooves using a dicer. Since the Au PHS layers are not present opposite the dicing grooves, no burr is produced on the rear surface of the semiconductor chip.
In the semiconductor chips produced according to the above-described method, however, portions of the plated Ni layer remaining at opposite sides of the chip are unfavorably in contact with bonding wires when the chip is mounted on a chip carrier, resulting in a short circuit that reduces the reliability of the device. In addition, when the surface of the wafer is adhered to a glass plate, the wafer is not parallel to the glass plate due to the plated Ni layers in the grooves, and a stress is applied to the Ni layers from the glass plate, cracking the wafer.